1. Field of the Invention
The present invention relates to a data processor, more particularly, to a data processor which is provided with either of cache memory, instruction queue, instruction pipelines, and branch prediction system, or a plurality of these, or all of these.
2. Description of the Prior Art
FIG. 1 denotes the simplified block diagram of memory hierarchy shown in "MICRO", August, 1987, a publication of IEEE, which incorporates CPU (central processing unit) 1, cache memory 2, main memory 3, and secondary storage 4, which are respectively installed in the hierarchical order.
FIG. 2 denotes the simplified block diagram of the data processor introduced in "MICRO", August, 1987, cited above, which represents the constitution of the pipeline system of the CPU 1, where the pipeline system incorporates pre-fetch unit 5 of cache memory 2, prefetch unit 6 of the CPU 1, decode control unit 7, and the execution unit 8, respectively. FIG. 3 denotes the schematic diagram of the address translation mechanism shown in "MICRO", March, 1987.
Next, operations of the conventional data processor cited above for example are described below.
First, a consideration is given to a case of operating the data processor shown in FIG. 1, in which the program shown in FIG. 4 is executed by the CPU 1 having the pipeline system shown in FIG. 2. This program features the following:
When executing the program shown in FIG. 4, after establishing the branch condition B2, the operation loop constituted by the first and second instructions I1 and I2 is repeatedly executed until the branch condition B1 is established. Then, after establishing the branch condition B1, the operation loop is discontinued to allow other processes to be executed. In other words, even if the branch condition B1 is established, the program allow the looped operation to be continuously executed until the branch condition B2 is established.
When the branch condition B2 is established while the execution of the program shown in FIG. 4 is underway, the CPU 1 then switches its control over to the instruction which designates rewriting of the no operation instruction into the conditional branch instruction judging the branch condition B1. As a result, the no operation instruction is converted into the conditional branch instruction which judges the branch condition B1, and then, the first and second instructions I1 and I2 are repeatedly executed until the branch condition B1 is eventually established.
Also, when operating the data processor shown in FIG. 1, if either the CPU 1 or the bus master rewrites a region of the main memory 3 previously cached to cache memory 2, without rewriting the corresponding region of the cache memory 2, the data stored in the main memory 3 and cache memory 2 may not correctly match each other. To prevent this problem, the operating system invalidates the entry of cache memory 2 corresponding to the changed region of the main memory.
Alternatively, when operating the address translation system shown in FIG. 3, if either the value of segment register or the access rights are changed by execution of instructions, like the above case, the operating system then identifies it and invalidates the data thus previously cached.
Since any of the conventional data processors employs a typical constitution mentioned above, if the pipeline incurs conflict by rewriting of instruction, change of stored contents in the main memory and the contents of the address translation mechanism except for using hardware to detect occurrence of conflict, any conventional data processor cannot judge whether the program is correctly executed, or not.